Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, in particular, to an insulated gate field effect transistor of a thin film type formed on an insulating surface which may be a surface of an insulating substrate such as glass or an insulating film such as silicon oxide formed on a silicon wafer. Specifically, the present invention is applicable to a manufacture of a TFT (thin film transistor) formed on a glass substrate of which glass distortion temperature is 750.degree. C. or lower. The present invention further relates to a semiconductor integrated circuit which utilizes TFTs on an insulating surface which are formed through a process at a process temperature 650.degree. C. or lower. The semiconductor integrate circuit of the present invention is suitable as an active matrix of a liquid crystal display, a driving circuit of an image sensor, three dimensional integrated circuit, or SOI integrated circuit or a conventional semiconductor integrated circuit such as microprocessor, microcomputer, micro-controller, or semiconductor memory etc. In particular, the present invention is advantageous for a monolithic type active matrix device in which an active matrix circuit and a peripheral driving circuit are formed on a substrate.
Recently, formations of insulated gate field effect semiconductor devices (MOSFET) on insulating substrates have been well studied. The formation of a semiconductor integrated circuit on an insulating substrate is advantageous for improving the operational speed of the circuit because there is no stray capacitor between the insulating substrate and wirings thereon while it exists in the case of a conventional semiconductor integrated circuit which employs a semiconductor substrate. The MOSFET which is formed on an insulating substrate and has an active region in a thin film form is called a thin film transistor (TFT).
Also, there is known a device in which a semiconductor integrated circuit is formed on a transparent substrate, for example, an optical device such as a liquid crystal display or an image sensor. Since these devices needs to be formed on a large area the TFT producing process needs to be done at a lower temperature. Further, since a device having a number of external terminals on a substrate has a difficulty in connecting said external terminals to external circuits, it has been suggested that the circuits corresponding those external circuits are monolithically formed on the same insulating substrate. FIG. 7 shows a block diagram of an example of such a monolithic type integrated circuit. In the figure, a monolithic type active matrix circuit is shown. On one substrate 7, an active matrix circuit 3, peripheral driving circuits 1 and 2 and bus lines 5 and 6 for connecting the active matrix circuit and the peripheral driving circuit. The active matrix circuit 3 includes a number of pixels 4 each of which comprises a TFT 8, pixel electrode 9 connected to an optical modulating medium 10 such as liquid crystal. In this structure, the above mentioned problem reducing the connection is avoided.
However, the electrical characteristics needed for TFTs of the driving circuit is generally different from that needed for TFTs of the active matrix circuit. For example, the active matrix circuit needs to have a sufficiently low leak current (off current) property when a reverse bias voltage is applied to a gate electrode. On the other hand, the peripheral driving circuit is required to have a sufficiently high mobility. If a monolithic active matrix device having more than 1000 scanning lines is to be formed, those TFTs in the peripheral driving circuit must have a mobility higher than 150 cm.sup.2 /Vs and an ON/OFF ratio of a drain current in the active matrix circuit must be 7 digits or more. It was almost impossible to achieve these properties simultaneously in the case of using a non-single crystalline semiconductor for the TFTs.
Crystalline TFTs have been proposed to be used for an active matrix liquid crystal device or an image sensor device. FIGS. 3A-3F are cross sectional views showing an example of a manufacturing method of a TFT in accordance with a prior art.
Referring to FIG. 3A, a base film 302 and an active layer 303 of crystalline silicon are formed on a substrate 301. An insulating film 304 is formed on the active layer using silicon oxide or the like.
Then, a gate electrode 305 is formed of phosphorous doped polysilicon, tantalum, titanium, or aluminum, etc. With this gate electrode used as a mask, an impurity element (e.g. phosphorous or boron) is doped into the active layer 303 by an appropriate method such as ion-doping in a self-aligning manner, thereby, forming impurity regions 306 and 307 containing the impurity at a relatively lower concentration and therefore having a relatively high resistance. These regions 306 and 307 are called a high resistance region (HRD: High Resistivity Drain) by the present inventors hereinafter. The portion of the active layer below the gate electrode which is not doped with the impurity will be a channel region. After that, the doped impurity is activated using laser or a heat source such as a flush lamp. (FIG. 3B)
Referring to FIG. 3C, an insulating film 308 of silicon oxide is formed through a plasma CVD or APCVD (atmospheric pressure CVD), following which an anisotropic etching is performed to leave an insulating material 309 (side spacer) adjacent to the side surfaces of the gate electrode as shown in FIG. 3D.
Referring to FIG. 3E, using the gate electrode 305 and the side spacer 309 as a mask, an impurity is introduced by ion doping or the like in order to form impurity regions 310 and 311 having a higher impurity concentration within the active layer 303. The impurity regions 310 and 311 have a low resistivity and are to become source and drain regions. Accordingly, there are two independent steps of introducing an impurity to the active layer and a step of an anisotropic etching between the two impurity introducing steps.
Then, the doped impurity is activated by means of a laser or a flush lump. Finally, as shown in FIG. 3F, an interlayer insulating film 312 is formed following which contact holes are formed on the source and drain regions through the interlayer insulating film. Further, through the contact holes, electrode/wirings 313 and 314 are formed from a metallic material such as aluminum.
The foregoing process was achieved pursuant to the known LDD technique for a conventional semiconductor integrate circuit and this method has some disadvantages for a thin film process on a glass substrate as discussed below.
Initially, it is necessary to activate the added impurity element with laser or flush lamp two times. Moreover, there exists a step of an anisotropic etching between these steps so that it is necessary to take out a substrate from a vacuum chamber. For this reason, the productivity is lowered. In the case of a conventional semiconductor circuit using a semiconductor substrate, the activation of an impurity can be carried out by a heat annealing at one time after completely finishing the introduction of the impurity (namely, after a step corresponding to FIG. 3F.)
However, in the case of forming TFTs on a glass substrate, the high temperature of the heat annealing tends to damage the glass substrate. Therefore, the use of laser annealing or flush lamp annealing is necessary. However, these annealing is effected on the active layer selectively, that is, the portion of the active layer below the insulating material (side spacer) 309 is not annealed, for example. Accordingly, the annealing step should be carried out at each time after an impurity doping is done.
Also, it is difficult to form the insulating material 309 accurately. Generally, the insulating film 308 is as thick as 0.5 to 2 .mu.m while the base film 302 on the substrate is 1000-3000 .ANG.thick. Accordingly, there is a danger that the base layer 302 is unintentionally etched and the substrate is exposed when etching the insulating film 308. As a result, a production yield can not be increased because substrates for TFTs contain a lot of elements harmful for silicon semiconductors.
Further, it is difficult to control the thickness of the insulating material 309 accurately. The anisotropic etching is performed by a plasma dry etching such as a reactive ion etching (RIE). However, because of the use of a substrate having an insulating surface as is different from the use of a silicon substrate, the delicate control of the plasma is difficult. Therefore, the formation of the insulating material 309 is difficult.
Since the above HRD should be made as thin as possible, the foregoing difficulty in precisely controlling the formation of the insulating material 309 makes it difficult to mass produce the TFT with a uniform quality.